Conference Publications of Dr. Mohd. Hasan

 

  1. Mohd. Hasan, “ Low power design issues in CMOS” in International Conference on Emerging Techniques in Electronics, Computing, Embedded Systems and VLSI, 20-21, March, 2008, PVDDP College of Engineering, Ahmednagar, India.
  2. A.K. Kureshi and Mohd. Hasan , “Leakage Analysis of CNFET Based Basic Digital Building Blocks”, published in the proceedings of International Conference on Emerging Techniques in Electronics, Computing, Embedded Systems and VLSI, 20-21, March, 2008, PVDDP College of Engineering, Ahmednagar, India.
  3. Tarun Agarwal, Anurag Sawhney, A.K. Kureshi and Mohd. Hasan, “ Subthreshold operation of MCML gates” accepted for presentation in International Conference on Communication Engineering and Computing”, Kualalampur, Malaysia.
  4. A.K. Kureshi and Mohd. Hasan, “ Leakage estimation and minimisation of CLB in FPGA” accepted for presentation in International Conference on Communication Engineering and Computing”, Kualalampur, Malaysia.
  5. Mohd. Tauheed Khan and  Mohd. Hasan , “A novel architecture of the 2D wavelet transform”, National Conference on Control and Instrumentation, National Institute of Technology, Kurukshetra, India, pp. 12-19, 29-30 Dec.2007.
  6. A.K. Kureshi, Naushad Alam and Mohd. Hasan, “Subthreshold Field programmable Gate Arrays”, Proceedings of MTECS-2008, 8-9 March, 2008,  Aligarh.
  7. Naushad Alam and Mohd. Hasan, “Comparison of Hybrid-CMOS Adders with static CMOS Adder in deep submicron Technology” Proceedings of MTECS-2008, 8-9 March, 2008, Aligarh.
  8. Naushad Alam, A.K. Kadir and Mohd. Hasan, “Analysis and Comparison of Subthreshold 1-Bit Full Adder Cells” accepted in IEEE International Conference and Colloquim SPIT-IEEE Colloquim, February, 4-5, 2008, Mumbai, India.
  9. A.K. Kureshi, Naushad Alam and Mohd. Hasan, “A novel low power high speed FPGA routing interconnects”, accepted in IEEE International Conference and Colloquim SPIT-IEEE Colloquim, February, 4-5, 2008, Mumbai, India.
  10. N. Alam, A.K. Kureshi and M. Hasan, “Subthreshold CMOS full adder for ultra low power operation”, International Conference on Systemics, Cybernetics and Informatics (ICSCI-2008), pp. 48-51, January 02-05, 2008, India. (Best Paper Award)
  11. A.K. Kureshi, N. Alam, and M. Hasan, “Low power Field programmable Interconnects”, International Conference on Systemics, Cybernetics and Informatics, pp. 52-55, January 02-05, 2008, India.
  12. K. A. Kadir and M. Hasan, “Leakage Power and Delay Optimization of FPGA Interconnects” accepted in an International Conference on Signal Processing, Communications and Networking (ICSCN 2008) Jan 4-6, 2008.
  13. K. A. Kadir and M. Hasan, “Static leakage power estimation and reduction techniques for SRAM cell” National Systems Conference (NSC-2007), pp. 34-35, 15-16 December, 2007, Manipal University.
  14. M. Asim Saeed, M. Hasan and Nesear Ahmad, “High speed optimized reconfigurable architecture of a Fuzzy logic controller” IET-UK International Conference on Information and Communication Technology in Electrical Sciences”, vol. II, pp. 558-561, 20-22, December 2007.
  15. M. Hasan, “Low Power design Issues in deep submicron” in National Conference on Nano, Bio and Information Technology Integration, March 23-25, 2007.
  16. Kureshi Kadir and Mohd. Hasan, "A study of different circuit level techniques for low leakage SRAM cell", Proceedings of National Conference on advanced computing & computer network NCACCN-2007, pp. 438-441, March 9-10, 2007.
  17. W. Han, A. T. Erdogan, T. Arslan, and M. Hasan, ‘Low Power Commutator for Pipelined FFT Processors’, IEEE International Symposium on Circuits and Systems, Vol. 5. pp: 5274–5277,  May, 2005.
  18. W. Han, A. T. Erdogan, T. Arslan, and M. Hasan, ‘Multiplier-Less based Parallel-Pipelined FFT Architectures for Wireless Communication Applications’ , IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2005) held in Philadelphia, USA, pp. V/45-V/48, 19-23 March, 2005.
  19. W. Han, A. T. Erdogan, T. Arslan, and M. Hasan, ‘The Development of High Performance FFT IP Cores through Hybrid Low Power Algorithmic Methodology’, Asia and South Pacific Design Automation Conference 2005 (ASP-DAC 2005) held in Shanghai, China, pp. 549-552, January 18-21, 2005.
  20. W. Han, T. Arslan, A.T. Erdogan and M. Hasan , ‘A novel low power pipelined  FFT based on subexpression sharing for wireless LAN applications’, IEEE Workshop on Signal and Image processing in Austin, Texas, USA, pp. 83-88, Oct., 2004
  21. M. Hasan, T. Arslan and J. Thompson, ‘A Delay spread based low power reconfigurable FFT processor architecture for wireless receivers’, International Symposium on SoC in Finland, pp. 135-138, November, 2003.
  22. M. Hasan, T. Arslan and J. Thompson, ‘A Novel Low Power Pipelined Architecture for a MC-CDMA receiver’, 3rd IEEE International Symposium on Image and Signal processing and Analysis, Part-II, pp. 1048-1053, September, 2003.
  23. M. Hasan and T. Arslan, ‘A Triple Port RAM Based Low Power Commutator Architecture for a Pipelined FFT Processor’, IEEE International Symposium on Circuits and Systems, vol. 5, pp. 353-356, May, 2003.
  24. M. Hasan and T. Arslan, ‘A coefficient memory addressing scheme for VLSI implementation of FFT processors’, IEEE International Symposium on Circuits and Systems, Volume: 4,  pp. 850-853, May, 2002.

  25. M. Hasan and T. Arslan, ‘FFT coefficient memory reduction technique for OFDM Applications’,  IEEE International Conference on Acoustics, Speech and Signal processing, Volume: 1, pp. 1085-1088, May 2002.

  26. A.T. Erdogan, M. Hasan and T. Arslan, ‘A low power FIR filtering core’, International Conference on ASIC/SoC , pp. 271-275, September, 2001.

  27. M. Hasan and S.A.Abbasi, ‘Programmable Logic Based Implementation of Digital Systems’, Proc. National symposium on design of electronics systems (NSDES) – 97, Aligarh, India, pp.279–84, 1997.

  28. M. Hasan and S. A. Abbasi, ‘Introduction to High Level Design of Digital Systems’, Proc.   NSDES – 97, Aligarh, India.  pp.297–302, 1997.

  29. M. Hasan and S. A. Abbasi, ‘A CAD Tool for an Automatic Design of a Fixed Topology CMOS Op-Amp’, Proc. National systems conference (NSC)-96, Thiruvanthapuram, pp. 92-96, December, 1996.

  30. M. Hasan and S. A. Abbasi, ‘Development of intelligent auxiliary CAMAC crate controller’, Proc. NSC-96, Thiruvanthapuram, India, pp. 87-91, December, 1996.

  31. V. Mohan, M. Hasan and S. A. Abbasi, ‘A New Interactive CAD Tool for IC Layout Design and Verification’, 6th International Symposium on IC Technology, Systems and Applications (ISIC-95), Singapore, pp. 87-91, September, 1995.

  32. G. Sharma, M. Hasan and S. A. Abbasi, ‘A CAD tool for an automatic optimised PLA based combinational  and Finite state machine layout generator’ Proc., NSC-95, Coimbatore, pp. 77-81, 1995.

  33. A. S. Khan and M. Hasan, ‘A CAD tool for two dimensional placement problem in VLSI design’, Proc. of Seminar on Electronic systems and applications, Roorkee, India, pp. 257-260, March, 1994.

  34. D. Solanki  and M. Hasan, ‘A new multilingual editor implemented only for Hindi language’, Proceedings  of the Eighteenth National systems conference (NSC-94), Agra, India, pp. 87-91, January , 1994.